【应用手册】Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design

【应用手册】Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design
The Altera® RapidIO interoperability reference design provides a sample interface between
the Altera RapidIO MegaCore® function configured on an Arria II GX device, and the Texas
Instruments TMS320TCI6488 Communications Infrastructure Digital Signal Processor
(TI 6488 DSP or TI 6488). Altera offers this reference design to demonstrate the installation
and operation of Altera’s RapidIO MegaCore function with the TI 6488. The reference design
enables you to evaluate the RapidIO MegaCore function for integration into an Altera FPGA.
In addition to demonstrating basic interoperability, the design includes support to measure
link utilization at all data rates, for all supported packet sizes. The statistics support helps
you to determine the optimal payload size for transfers across the Serial RapidIO link from
the Arria II GX device to the TI 6488 DSP for the three baud rates available in the Quartus II
software v9.0. Because the TI6488 supports only 1× link modes, the design tests only 1×
modes.
Arria II GX RapidIO Interoperability with
TI 6488 DSP Reference Design

December 2009 AN599-1.0




Introduction
The Altera RapidIO interoperability reference design provides a sample interface between
the Altera RapidIO MegaCore function configured on an Arria II GX device, and the Texas
Instruments TMS320TCI6488 Communications Infrastructure Digital Signal Processor
(TI 6488 DSP or TI 6488). Altera offers this reference design to demonstrate the installation
and operation of Altera’s Rap