PLL抖动和CAN协议及其影响

Phase Locked Loop (PLL) circuits are increasingly
used in microcontrollers to achieve higher internal
clock frequencies. This allows better performance
while reducing overall noise. Several of Microchip’s
PIC18 microcontrollers feature 4x PLLs in their clock
generation circuits. This makes it possible to generate
an internal 40 MHz clock from an external 10 MHz
crystal.
One drawback in the use of PLL circuits is that they
create a small, but still measurable level of transient
phase shifts, or jitter . This Technical Brief shows the influ-
ence of PLL jitter on Microchip’s PIC18 microcontrollers,
how it affects the overall clock of the microcontroller and
how the combined effects of jitter and crystal drift are well
below the CAN 2.0 specification.
TB078
PLL Jitter and Its Effects in the CAN Protocol

Author: Caio Gübel EXTERNAL CLOCK, INTERNAL
Microchip Technology Inc. CLOCK AND MEASURABLE JITTER
The microcontroller clock frequency generated from a
INTRODUCTION PLL circuit is subject to a jitter, also defined as Phase
Jitter or Phase Skew. For its PIC18 Enhanced micro-
Phase Locked Loop (PLL) circuits are increasingly