Design a Low-Jitter Clock for High-Speed Data Converters

Abstract: High-speed applications using ultra-fast data converters in their design often require an extremely clean clock signal to make sure an external clock source does not contribute undesired noise to the overal dynamic performance of the system. It is therefore crucial to select suitable system components, which help generate a low phase-jitter clock. The following application note serves as a valuable guide for selecting the appropriate components to design a low-phase noise PLL-based clock generator, suitable for ultra-fast data converters.

Maxim > App Notes > A/D and D/A CONVERSION/SAMPLING CIRCUITS HIGH-SPEED SIGNAL PROCESSING

Keywords: high-speed ADCs, high-speed analog to digital converter, PLL, VCO, phase-locked loop, voltage- Nov 20, 2001
controlled oscillator, low phase noise, low phase jitter, clock jitter, crystal oscillator, noise, SNR, spurious
components, analog digital, data converters

APPLICATION NOTE 800
Design a Low-Jitter Clock for High-Speed Data Converters

Abstract: High-speed applications using ultra-fast data converters in their design often require an extremely
clean clock signal to make sure an external clock source does not contribute undesired noise to the overal
dynamic performance of the system. It is therefore crucial to select suitable system components, which help
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