Xilinx constraints

Xilinx_constraints
Constraints
Practical Design for Xilinx!!

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Practical Design for Xilinx, Section 7,
12/29/98 Page 1
 When to use Timing Constraints?
Constraints add to run time, so don’t use them unless you need to
Faster designs need constraining
― it depends on the speed grade of the device selected, but in general, any design with a
clock speed of 50MHz or less and a reasonable number of logic levels (7 or less), doesn’t
need timing constraints
― designs over 50MHz should use timing cons