智能时钟门控减少开关电源

赛灵思公司提供自动化，精细粒度时钟门控解决方案，最多可减少30％的Virtex - 6，Spartan- 6，KINTEX- 7，和Virtex- 7 FPGA设计的动态功耗。
White Paper: Virtex-6, Spartan-6, Kintex-7, and Virtex-7 FPGAs




WP370 (v1.3) March 1, 2011



Reducing Switching Power
with
Intelligent Clock Gating
By: Frederic Rivoallon




Xilinx delivers the first automated, fine-grain
clock-gating solution that can reduce dynamic
power by up to 30% in Virtex-6, Spartan-6,
Kintex-7, and Virtex-7 FPGA designs.