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异步FIFO结构

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Expert Verilog, SystemVerilog & Synthesis Training




Simulation and Synthesis Techniques for Asynchronous
FIFO Design



Clifford E. Cummings, Sunburst Design, Inc.
cliffc@sunburst-design.com




ABSTRACT

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a
FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design
techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still
make it difficult to properly synthesize and analyze the design.
This paper will detail one method that ……
标签:FIFO异步
异步FIFO结构
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