资料介绍
C8051F06x C8051F060/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals High Speed 8051 C Core
- Two 16-Bit SAR ADCs - Pipelined instruction architecture; executes 70% of
16-bit resolution instruction set in 1 or 2 system clocks
±0.75 LSB INL, guaranteed no missing codes - Up to 25 MIPS throughput with 25 MHz clock
Programmable throughput up to 1 Msps
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