e-C8051F0xx.pdf

e-C8051F0xx.pdf
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Mixed-Signal 32KB ISP FLASH MCU Family
a
ANALOG PERIPHERALS HIGH SPEED 8051 C CORE
- SAR ADC - Pipelined Instruction Architecture; Executes 70% of
12-Bit (C8051F000/1/2, C8051F005/6/7) Instruction Set in 1 or 2 System Clocks
10-bit (C8051F010/1/2, C8051F015/6/7) - Up to 25MIPS Throughput with 25MHz Clock
±1LSB INL;