[2001]A novel CMOS charge-pump circuit with positive feedback for PLL applications

The design and simulation of a
novel CMOS charge-pump topology for RF
frequency synthesizers is presented. Based on
positive feedback and current reuse, the switching
speed is increased and the power consumption is
reduced. Simulation results, shows that the
structure is suited for low-voltage and high
frequency applications
Instituto Tecnológico de Chihuahua ELECTRO 2001




A NOVEL CMOS CHARGE-PUMP CIRCUIT WITH POSITIVE FEEDBACK FOR
PLL APPLICATIONS

Esdras Juárez-Hernández and Alejandro Díaz-Sánchez
Instituto Nacional de Astrofísica, Optica y Electrónica
Luis Enrique Erro #1 Sta. Ma. Tonantzintla. Puebla-México.

Instituto Tecnológico de Puebla
Avenida Tecnológico número 420, Colonia Maravillas, Puebla, Pue.
E-mail: esdrasj@susu.inaoep.mx, adiazsan@inaoep.mx


ABSTRACT: The design and simulation of a DWN are low (third state), the net curren