[1997]Optimum phase-acquisition technique for charge-pump PLL

Abstract—In this paper, we propose a new optimum phase-
acquisition algorithm controlling the loop gain of a charge-
pump PLL (CP-PLL) in the sense of the MMSE criterion. A
set of recursive difference equations minimizing rms jitter of
output phase is derived to obtain an optimum gear-shifting
sequence with a zero-phase start (ZPS) assumption. It is shown
that the optimum gear-shifting sequence is independent of the
variance of the input phase jitter. A procedure for applying
this sequence to the design of CP-PLL circuits is described.
Both behavioral simulation and HSPICE circuit-level simulation
demonstrate that the proposed design leads to an efficient CP-
PLL having both fast acquisition and significant jitter reduction
characteristics. The optimal gear-shifting CP-PLL outperforms
the conventional CP-PLL’s. These methods can be used for clock
recovery applications such as data communication receivers, disk
drive read/write channels, and local area networks, as well as for
other applications requiring very short initial preamble periods.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS―II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 9, SEPTEMBER 1997 729




Optimum Phase-Acquisition Technique
for Charge-Pump PLL
Gyoung-Tae Roh, Yong Hoon Lee, and Beomsup Kim, Senior Member, IEEE



Abstract― In this paper, we propose a new optimum phase- characteristic and low jitter [10]