Multimedia Decoder Using the Nios II Processor (PDF)

Multimedia Decoder Using the Nios II Processor (PDF)
Multimedia Decoder Using the Nios II Processor




Third Prize


Multimedia Decoder Using the Nios II
Processor

Institution: Indian Institute of Science

Participants: Mythri Alle, Naresh K. V., Svatantra Singh

Instructor: S. K. Nandy




Design Introduction
Our design target was to build a low-cost, high-performance H.264 decoder with a prototype H.264
decoder created using multiple small FPGAs. H.264 is a computationally complex, advanced video
standard for achieving high compression ratios. To cater to the needs of high throughput applications
such as HDTV, which requires 216,000 macroblocks/second of throughput, designers usually advocate
a hardware implementation. Our proposed design is targeted at consumer