资料介绍
74LS256.pdf 54LS256 DM74LS256 Dual 4-Bit Addressable Latch
June 1989
54LS256 DM74LS256
Dual 4-Bit Addressable Latch
General Description
The ’LS256 is a dual 4-bit addressable latch with common could impose a transient wrong address Therefore this
control inputs these include two Address inputs (A0 A1) should be done only while in the memory mode (E e CL e
an active LOW enable input (E) and an active LOW Clear HIGH)
input (CL) Each latch has a Data input (D) and four outpu
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