资料介绍
74LS164.pdf 54LS164 DM54LS164 DM74LS164 8-Bit Serial In Parallel Out Shift Registers
June 1989
54LS164 DM54LS164 DM74LS164
8-Bit Serial In Parallel Out Shift Registers
General Description Features
These 8-bit shift registers feature gated serial inputs and an Y Gated (enable disable) serial inputs
asynchronous clear A low logic level at either input inhibits Y Fully buffered clock and serial inputs
entry of the new data and resets t
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