资料介绍
CPU配置FPGA广东省深圳市深南大道创展中心 1007 房间骏龙科技有限公司宋士权
Altera 中国区代理 -----骏龙科技有限公司 Field Application Engineer: sun song 收集整理
TEL: 13823390270 ; E-mail:suns@cytecht.com
8051 汇编语言 :
;How fast is the DCLK can go?
;in the range of 4 ~ 6 MHz
base_address equ 0 ; if define 00000h, this program compile ROM image.
; Internal RAM usage start at 20h
; address 20h-2fh are bit addressable area
; address 30h-7fh are byte addressable area
; P1.0 - DCLK (output)("0")
; P1.1 - CONF_DONE (input) ("1")
; P1.2 - nCONFIG (output) ("0")
; P1.3 - nSTATUS (input) ("1")
; P1.4 - DATA0 (output) ("0")
; P1.5 - Done (output) ("0")
; PROGRAM SEGMENT DEFINE
org 0h
power_up: ljmp start
org 30h
; INITIALIZE THE 82c31 INTERNAL REGISTER
start: clr psw.4 ; select bank 0 (00-07h)
clr psw.3
clr ea ; disable the global interrupt
mov sp,#50h ; set
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