资料介绍
触发器_ Homework_6
The input signals shown in Fig. 1 are applied to the
master-slave JK flip-flop of Fig. 2 when initially in its
0-state. Sketch the QM and QS output signals.
Assume all timing constraints are satisfied.
Deadline: March 30
2004-3-23 Copyright reserved by Prof. Luo 194
Homework_6
J
K
C
Fig.1 t
QM QS
J S Q S Q Q
Clock( C ) C QM C QS
K R R Q Q