资料介绍
时钟分频电路实现精讲 Clock Dividers Made Easy
Mohit Arora
Design Flow and Reuse (CR&D)
ST Microelectronics Ltd
Plot No. 2 & 3, Sector 16A
Noida-201301, India
(www.st.com)
ABSTRACT
Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is
necessary to generate a 50% duty cycle frequency even when the input clock is divided by an
odd or non-integer number. This paper talks about implementation of unusual clock dividers.
The paper starts up with simple dividers where the clock is divided by a
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