LowPowerRFCircuitDesigninStandardCMOSTechnology

A Springer new book in 2011/E: Low Power RF Circuit Design in Standard CMOS Technology.

1 Introduction.....................................................................................................1
1.1 Recent Evolution of Personal Communication Devices.......................... 1
1.2 Examples of Applications ....................................................................... 2
1.3 Frequency Allocation for the Next Wireless Applications...................... 4
1.4 Common Requirements to Current Handheld Devices:
OFDM Modulations................................................................................. 5
1.5 Low Power RFIC Design ........................................................................ 7
1.5.1 CMOS Technology ....................................................................... 8
1.5.2 Low Power Design Techniques for Analog Circuits..................... 9
2 Power Considerations in Analog RF CMOS Circuits...............................11
2.1 Sources of Power Dissipation................................................................ 11
2.1.1 Dynamic Switching Power......................................................... 11
2.1.2 Leakage Current Power .............................................................. 12
2.1.3 Short-Circuit Current Power ...................................................... 13
2.1.4 Static Biasing Power .................................................................. 13
2.2 Limits in Power Dissipation.................................................................. 14
2.2.1 Fundamental Limits.................................................................... 14
2.2.2 Practical Limits .......................................................................... 16
2.3 VDD Downscaling ................................................................................ 16
2.3.1 Threshold Voltage ...................................................................... 17
2.3.2 Sub-threshold Region................................................................. 18
2.3.3 MOS Transistor Speed and Bandwidth ...................................... 19
2.3.4 Analog Switches......................................................................... 20
2.3.5 Transistor Stacking..................................................................... 21
2.3.6 Dynamic Range .......................................................................... 22
2.3.7 Power Consumption ................................................................... 23
References ............................................................................................................ 23
3 Impact of Architecture Selection on RF Front-End
Power Consumption.....................................................................................25
3.1 Front-End Challenges............................................................................ 25
3.1.1 Image Rejection.......................................................................... 26
3.1.2 DC Offsets.................................................................................. 26
3.1.3 I/Q Mismatch.............................................................................. 28
3.1.4 Even-Order Distortion................................................................ 29
3.1.5 Flicker (1/f) Noise ...................................................................... 30
3.1.6 Sensitivity and Noise Figure (NF).............................................. 31 X Contents
3.1.7 Linearity ..................................................................................... 31
3.2 Superheterodyne Architecture............................................................... 33
3.3 Double Conversion Architecture........................................................... 33
3.4 Image-Rejection (Hartley, Weaver) Architecture ................................. 35
3.4.1 Hartley Architecture................................................................... 35
3.4.2 Weaver Architecture .................................................................. 36
3.5 Direct Conversion Receiver Architectures............................................ 37
3.5.1 Zero IF Architecture................................................................... 37
3.6 Low IF Architecture .............................................................................. 38
References ............................................................................................................ 39
4 Technology Structural Alternatives in Standard CMOS Technologies
for Low-Power Analog Design.....................................................................41
4.1 Threshold Voltage (V T )......................................................................... 41
4.1.1 Multiple-Threshold Transistors .................................................. 41
4.1.2 Variable-Threshold Transistors .................................................. 45
4.2 Gate Length Downsaling....................................................................... 47
4.3 Silicon-on-Insulator (SOI)..................................................................... 51
4.3.1 Technology Description ............................................................. 51
4.3.2 SOI Technology Benefits in Analog Circuits............................. 54
4.3.3 SOI Design Issues Not Present in CMOS Bulk.......................... 55
4.3.4 SOI and IC Design for Radio Frequency ................................... 57
References ............................................................................................................ 58
5 Schematic Design Techniques for Power Saving in RF.............................61
5.1 Current Reuse........................................................................................ 61
5.1.1 Operation Principle .................................................................... 61
5.1.2 Basic Implementations ............................................................... 65
5.2 Multi-VDD............................................................................................ 72
5.3 Power Gating......................................................................................... 74
5.4 Multiple Channel Length ...................................................................... 76
5.5 Gate Biasing .......................................................................................... 77
5.5.1 Strong Inversion ......................................................................... 77
5.5.2 Weak Inversion .......................................................................... 79
5.5.3 Moderate Inversion .................................................................... 79
5.5.4 Moderate and Weak Inversion Benefits ..................................... 80
References ............................................................................................................ 81
6 RF Amplifier Design.....................................................................................87
6.1 Basic Stages Fundamentals ................................................................... 87
6.1.1 NMOS Transistor Basic Expressions ......................................... 88
6.1.2 Common Source Configuration.................................................. 90
6.1.3 Common Drain Configuration.................................................... 92
6.1.4 Common Gate Configuration ..................................................... 94
6.1.5 Comparison of the Basic Configurations.................................... 95 Contents XI
6.2 Amplifier Topologies ............................................................................ 96
6.2.1 Cascoded Amplifier.................................................................... 96
6.2.2 Tuned Load: LC-Tank................................................................ 97
6.2.3 Active Load ................................................................................ 98
6.2.4 Negative Feedback Estructures .................................................. 99
6.3 LNA Low Power Design Considerations ............................................ 103
6.3.1 Inductive Degeneration ............................................................ 104
6.3.2 Q - Passive Devices.................................................................. 104
6.3.3 Transistor Polarization ............................................................. 105
6.3.4 Current Reuse........................................................................... 105
6.3.5 Impedances Matching............................................................... 105
6.3.6 Cascode .................................................................................... 105
6.4 Low-Power LNA Design Examples.................................................... 106
6.4.1 Example 1: Low-Power LNA for DVB-T/H............................ 106
6.4.2 Example 2: Low-Power LNA for the 5GHz U-NII Band......... 116
References .......................................................................................................... 126
7 Mixer Design...............................................................................................129
7.1 Mixer Fundamentals........................................................................... 129
7.1.1 Conversion Gain / Loss ........................................................... 131
7.1.2 Linearity .................................................................................. 131
7.1.3 Noise Figure ............................................................................ 133
7.1.4 Impedance Matching and Port Isolation.................................. 133
7.2 Mixer Topologies ............................................................................... 134
7.2.1 Active Mixers.......................................................................... 134
7.2.2 Passive Mixers......................................................................... 137
7.3 Mixer Design Constraints................................................................... 139
7.3.1 Gain......................................................................................... 139
7.3.2 Linearity .................................................................................. 146
7.3.3 Noise ....................................................................................... 148
7.3.4 Bandwidth ............................................................................... 151
7.3.5 Impedance Matching and Port Isolation Considerations ......... 152
7.4 Low-Power Mixer Design Examples ................................................. 153
7.4.1 Example 1: Low-Power Low-Noise Mixer for DVB-T/H....... 153
7.4.2 Example 2: Low-Power Mixer for WLAN
(5GHz U-NII Band) ................................................................ 163
7.4.3 Example 3: Very Low-Power Passive Mixer for Wlan
(5GHz U-NII Band) ................................................................. 169
References .......................................................................................................... 175
8 Phase Locked Loop (PLL) Design.............................................................179
8.1 Frequency Synthesis Fundamentals .................................................... 179
8.1.1 Introduction to PLL.................................................................. 179
8.1.2 PLL Architectures .................................................................... 180
8.2 Phase-Frequency Detector (PFD) Design Constraints ........................ 185
8.2.1 Multipliers ................................................................................ 185 XII Contents
8.2.2 Exclusive-OR Logic Gate and Flip-Flops ................................ 186
8.2.3 PFD/CP .................................................................................... 188
8.3 Voltage-Controlled Oscillator Design Constraints.............................. 191
8.3.1 Functional Description ............................................................. 191
8.3.2 Voltage Controlled Oscillator Design Constraints ................... 192
8.4 High-Frequency Divider Design Constraints ...................................... 199
8.4.1 Frequency Dividers Basic Implementation .............................. 199
8.4.2 High Frequency Divider Architectures and Building Blocks... 200
8.5 Low-Power Design Examples ............................................................. 211
8.5.1 Example 1: Wideband VCO for DVB-H.................................. 212
8.5.2 Example 2. High FrequencyVCO............................................. 223
8.5.3 Example 3: High Frequency Divider and Dual-Modulus
Prescaler for WLAN (5GHz UNII Band) ................................ 228
References .......................................................................................................... 234