PCI Express™ Architecture Signaling Tutorial

PCI Express™ Architecture Signaling Tutorial
Jan/Feb 2003




PCI Express Architecture
Signaling Tutorial


Zale Schoenborn
Intel Corporation
Co-Chair, PCI Express Electrical WG
 Agenda
PCI Express Physical Layer (PHY)
Basics
Usages and requirements
Definitions
Signaling

PCI Express PHY Key Features
Logical Sub-block
Electrical Sub-block

Summary
 PHY Requirements & Usage
Chip-to-chip data
transfers through
4 layer FR-4 PCBs Desktop Mobile
Silicon: small area, Low Cost Low Cost
low power, In-the-box Focus Low Power
low manufacturing Chip-Chip Small Form Factors
costs Board-Board Docking

Low cost connec