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ASIC to FPGA 设计方法和指导

资料介绍
ASIC to FPGA 设计方法和指导
ASIC to FPGA Design
Methodology and Guidelines

October 2007, ver. 2.0 Application Note 311



Introduction The cost of designing ASICs is increasing every year. In addition to the
non-recurring engineering (NRE) and mask costs, development costs are
increasing due to ASIC design complexity. Issues such as power, signal
integrity, clock tree synthesis, and manufacturing defects can add
significant risk and time-to-market delays. FPGAs offer a viable and
competitive option to ASIC development by reducing the risk
标签:AlteraASICFPGAEDAPHYSPOCQuartus
ASIC to FPGA 设计方法和指导
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