An Accurate Control Loop Model for Current-Mode Step-Down Controllers

Peak current-mode control is preferred by power supply designers because it provides a first-order frequency response characteristic in the control-to-output transfer function. A control-loop design procedure based on the first-order model predicts a phase margin close to 90 degrees. It is found, however, that the phase margin obtained in practice is far less than 90 degrees depending on choice of crossover frequency, operating duty cycle, and amount of slope compensation used. This is due to the sampling effect of the control-loop current comparator. The following application note describes a control-loop design procedure for the MAX1954A current-mode controller that considers this sampling effect and accurately predicts phase margin. This analysis is not specific to the MAX1954A, however, and applies to most current-mode step-down ICs sold today.