资料介绍
FPGA—8051008051 IP Core
Bootstrap Demo Design - User Guide
Erfolg folgt Erfahrung
Implementing the MC8051 IP Core On A Cyclone Nios Board
First of all it is necessary to exchange the simulation models of all the memory blocks with
real memory that can be found inside the target FPGA. It is also recommended to implement a
PLL to get a clock signal with a lower frequency than that of the on-board oscillator. The
VHDL code for these entities is generated by the backend tool, i.e. Quartus II 4.0 for Altera
FPGAs.
Step 1: Choose the function that should be generated.
1. After starting Quartus II, launch the Megawizard
Plug-In Manager that is located in the Tools-Menu.
2. Select the function block that
should be generated.
我要上传