EDA_常见实例源程序代码vhdl

EDA_常见实例源程序代码vhdl


4.1 组合逻辑电路设计
4.1.1 基本逻辑??
library ieee;
use iee.std_logic_1164.all;
entity jbm is
port(a,b: in bit;
f1,f2,f3,f4,f5,f: out bit);
end jbm;
architecture a of jbm is
begin
f1<=a and b; --构成与门
f2<=a or b; --构成或门
f<=not a; --构成非门
f3<=a nand b; --构成与非??
f4<=a nor b; --构成异或??
f5<=not(a xor b); --构成异或非门即同??
end;

library ieee;
use ieee.std_logic_1164.all;
entity tri_s is
port(enable: in std_logic;
datain: in std_logic_vector(7 downto 0);
dataout: out std_logic_vector(7 downto0));
end tri_s;
architecture bhv of tri_s is
begin
process(enable,datain)
begin
if enable='1' then
dataout<=datain;
else
dataout<="ZZZZZZZZ";