资料介绍
interrupt handlerSystem Service - Interrupt Handler (V0.1)
By Shalyn Chua MediaTek Inc. Wireless Communications BU
Outline
An Introduction of interrupt controller
Interrupt sources Mapping of interrupts (prioritized) Interrupt Service Flow Customization API Registration and API
External interrupts
Usage of nIRQ
QA
An Introduction of Interrupt Controller (1/2)
ARM core,
Interrupt (IRQ)
Controlled by I-bit, and entry at 0x18. Controlled by F-bit, and entry at 0x1C. Reserved for future enhancement!
Fast Interrupt (FIQ)
MT6218B,
24 interrupt sources, numbered from 0 ~ 23. Interrupt numbered 0 not necessary the highest priority, depend on where it maps!
An Introduction of Interrupt Controller (2/2)
The highest priority interrupt is IRQ0, the lowest is IRQ1f, The mapp
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