TI high speed PCB layout desig...

TI High-Speed Board DesignHigh Speed Design Seminar 6HULDO *LJDELW 6ROXWLRQV

BuS Solutions

High-Speed Board Design
Bill Simms

Serial Gigabit Solutions

High Speed Design Seminar 6HULDO *LJDELW 6ROXWLRQV

High Speed Board Design
BuS Solutions

Layout and Routing Filtering Component Placement

07/22/1999

Serial Gigabit Solutions

High Speed Design Seminar 6HULDO *LJDELW 6ROXWLRQV

Board Stackups
BuS Solutions
2 G G S2 G S2 G G 3 P S2 G S2 G S2 S2 4 S2 S3 P P S3 G S3 5 6 7 8 9 10 Comments Difficult to maintain high signal impedance and low power impedance Lower Speed Design, poor power, high signal impedance Default critical signals on S2 only Default lower-speed signals to S2 only S5 G S4 S6 S4 S5 G S6 Default high-speed signals to S2-S3. Has poor power impedance Best for EMC Best for EMC. S4 susceptible to pow