资料介绍
阻抗控制和设计Controlled Impedance Design and Test
Intel Corporation
Intel’s
Labs
Agenda
zStatement
of Objective zBackground zAC Timing and Signal Quality zImpedance Fundamentals zDesign Guidelines zTesting Board Impedance (TDR) zSummary and Conclusions Intel’s
Labs
Objective
The objective of this presentation is to provide information to assist OEMs and PCB vendors to design and test motherboards which will meet a 28 (+/- 10%) impedance specification
Intel’s
Labs
Background
z Existing
motherboards are designed around 65 +/-15% z The new 28 +/-10% specification is required by the memory channel z Exceeding the specification results in additional channel timing error and reduced signal margin z Both effects may cause failures on the memory channel Intel’s
Labs
Signal Quality and Ti
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