首页|嵌入式系统|显示技术|模拟IC/电源|元件与制造|其他IC/制程|消费类电子|无线/通信|汽车电子|工业控制|医疗电子|测试测量
首页 > 分享下载 > 消费类电子 > Wrapping Transistor-Level HPSI...

Wrapping Transistor-Level HPSI...

资料介绍
AppNote_wrap_HSPICEWrapping Transistor-Level HPSICE IO Models for Use in Allegro PCB SI: Application Note
Product Version 15.2 June 2004

2004 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, t
标签:AppNoteHSPICE
Wrapping Transistor-Level HPSI...
本地下载

评论