Practical timing analysis

Practical timing analysisdesignfeature By Bob Kirstein, Stratus Engineering

MOST TECHNICAL LITERATURE ON HIGH-SPEED DESIGN FOCUSES ON TERMINATION, RINGING, AND CROSSTALK. DESPITE SIGNAL INTEGRITY’S IMPORTANCE, INADEQUATE TIMING MARGINS CAUSE MANY MORE ERRORS IN TODAY’S 100-MHz DIGITAL DESIGNS.

Practical timing analysis for 100-MHz digital designs
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s increasing chip complexity, high clock rates, and analog signal-integrity issues complicate digital design, time-to-market pressures continue to shorten development schedules. These factors present increasing challenges to digital-design engineers, who must spend more time understanding software and system-level issues and have less time for details such as timing analysis. Because you can’t ignore board-level propagation delays in today’s more-than-100-MHz designs,