Design Procedure for Two-Stage...

Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme1508

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS―I: REGULAR PAPERS, VOL. 52, NO. 8, AUGUST 2005

Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme
Jirayuth Mahattanakul, Member, IEEE, and Jamorn Chutichatuporn
Abstract―This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater exibility. In order to verify the viability of the proposed design step, SPICE simulation results