Parasitic inductance of a bypa...

Parasitic inductance of a bypass capacitorsignalintegrity By Howard Johnson, PhD

Parasitic inductance of a bypass capacitor

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ou can estimate the parasitic series inductance of a bypass capacitor in a multilayer board with solid power and ground planes. Use an approximation for

the inductance L1 due to the chip layout (Figure 1, green shaded region). Then, assuming that you have connected
and-ground bounce that your chip experiences but not the noise coupled onto the power and ground planes. The chip power-supply currents flowing through the impedances of L2 and L1 generate most of the high-frequency power- and ground-plane noise emanating from the structure in Figure 1. Power- and ground-plane noise in the frequency region that the bypass capacitors control is therefore proportional to L2L1. To compute L2 (blue region), assum