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锁相环培训资料

资料介绍
ADI Clock training materialThe World Leader in High-Performance High Performance Signal Processing Solutions

Understand Noise & Jitter in Clock Circuit Design

―Analog Devices Confidential Information―

Common Output Configuration

2

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LVPECL
Pros
Quasi-differential high slew rates can accept near/far termination fanout capability relatively “quiet” such that it doesn’t corrupt other signals easily

Cons
High Power “Requires” a bipolar device that is not available on CMOS processes

3

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LVDS
Pros
True differential Some variants can accept near/far termination “Quiet” such that it doesn’t corrupt other signals easily Low power

Cons
Low signaling (±0.4V) often does not yield highest slew rates at receiver resulting in higher noise than LVPECL Care needs to be taken to insure “aggress……
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锁相环培训资料
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