资料介绍
MAX1970019-3549; Rev 0; 2/05
KIT ATION EVALU E L B AVAILA
7.5Msps, Ultra-Low-Power Analog Front-End
General Description Features
Dual 10-Bit Rx ADC and Dual 10-Bit Tx DAC Ultra-Low Power 36.3mW at fCLK = 5.12Msps, Fast Mode 19.8mW at fCLK = 5.12Msps, Slow Mode Low Standby and Shutdown Current Integrated TD-SCDMA Filters with >55dB Stopband Rejection Excellent Dynamic Performance SINAD = 54.9dB at fIN = 1.87MHz (Rx ADC) SFDR = 76.5dBc at fOUT = 620kHz (Tx DAC) Excellent Gain/Phase Match ±0.22° Phase, ±0.02dB Gain (Rx ADC) at fIN = 1.87MHz at -0.5dBFS Three 12-Bit, 1s Aux-DACs Single-Supply Operation Multiplexed Parallel Digital I/O Serial-Interface Control Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx-Rx Disable Miniature 48-Pin Thin QFN Package (7mm x 7mm x 0.8mm)
MAX1
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