一个论文－A 2-5GHz Low Jitter 0.13u...

A 2-5GHz Low Jitter 0IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE

A 2-5GHz Low Jitter 0.13p.m CMOS PLL Using a Dynamic Current Matching Charge-pump and a Noise Attenuating Loop-Filter
Adrian Maxim
Integrated Products, 4201 Monterey Oaks #612, Austin TX 78749, Email: adrianmaxim@ieee.org

Abstract A low noise ring oscillator based PLL frequency synthesizer was realized for wideband tuner applications. The reference spurs are minimized using a fast reset, precharged phase-frequency-detector and a dynamic current matching charge-pump. The PLL has a single power supply, while a shunt regulator was used to bias the digital blocks without coupling noise to the analog supply. A two stage symmetric NFET load ring oscillator was used for both low phase noise and high frequency operation. A noise attenuating loop fi