资料介绍
PhaseLockedLoop_2006--DESIGNPHASE LOCKED LOOP DESIGN
by
Kristen Elserougi, Ranil Fernando, Luca Wei
SENIOR DESIGN PROJECT REPORT
Submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electrical Engineering School of Engineering Santa Clara University
Santa Clara, California June 20, 2006
Abstract Our team chose to do a complete mixed signal IC design process. With this purpose, we decided to design a Phase Locked Loop (PLL) because the design process would incorporate topics from digital, analog, IC design, and control systems theory. This range of topics is an adequate way to incorporate the primary electrical engineering theories into one project. A PLL is a closed loop frequency system that locks the phase of an output signal to an input reference signal. The term “loc
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