verilog_parameter

HDL_ParametersNew Verilog-2001 Techniques for Creating Parameterized Models (or Down With `define and Death of a defparam!)
Clifford E. Cummings Sunburst Design, Inc. cliffc@sunburst-design.com

Abstract
Creating reusable models typically requires that general-purpose models be written with re-definable parameters such as SIZE, WIDTH and DEPTH. With respect to coding parameterized Verilog models, two Verilog constructs that are over-used and abused are the global macro definition (`define) and the infinitely abusable parameter redefinition statement (defparam). This paper will detail techniques for coding proper parameterized models, detail the differences between parameters and macro definitions, present guidelines for using macros, parameters and parameter definitions, discourage the use of defparams,