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出绝招了----TSMC Reference Design ...

资料介绍
TSMC_3_0_Design_flow_diagramTSMC Hierarchical Design Flow Diagram

TSMC Hierarchical Design Flow Diagram / TSMC Reference Flow Release 3.0

Confidential-Security C

1

Prototyping

Hierarchical Timing Closure

Fullchip Verification

Netlist, Timing Constraint, Size

budgeting (PT) RC Correlation(FE->PC) full chip verification: IR analysis (Voltage Storm) DRC LVS (Calibre) Formal Verification (Formality, Verplex) xtalk (CeltIc)

RC Correlation (StarRCXT->Apollo->FE)

block frame view and pdb generation(APO) block preCTS implementation (PC): placement, timing optimization block timing model generation

flattened prototyping (FE)

floorplanning (FE) top preCTS implementation (PC): placement, timing optimization top level trial route (APO) top/block implementation (APO): CTS, track assign, SDF RC Correlation (APO->PC) b……
标签:Designdiagram
出绝招了----TSMC Reference Design ...
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