Verilog非阻塞性赋值

Verilog非阻塞性赋值Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
SNUG-2000 San Jose, CA Voted Best Paper 1st Place

Clifford E. Cummings

Sunburst Design, Inc.

ABSTRACT One of the most misunderstood constructs in the Verilog language is the nonblocking assignment. Even very experienced Verilog designers do not fully understand how nonblocking assignments are scheduled in an IEEE compliant Verilog simulator and do not understand when and why nonblocking assignments should be used. This paper details how Verilog blocking and nonblocking assignments are scheduled, gives important coding guidelines to infer correct synthesizable logic and details coding styles to avoid Verilog simulation race conditions.

1.0 Introduction
Two well known Verilog coding guidelines for modeling logic are: