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Art of Writing TestBenchesArt of Writing TestBenches
http://www.asic-world.com/verilog/art_testbench_writing.htmlJan-2-2006
Introduction Before you Start Example - Counter Code for Counter Test Plan Test Cases Writing TestBench Test Bench Test Bench with Clock gen Test Bench continues... Adding Reset Logic Code of reset logic Adding test case logic Test Case 1 - Asserting/ De-asserting reset Test Case 2 - Assert/ De-assert enable after reset is applied. Test Case 3 - Assert/De-assert enable and reset randomly. Adding compare Logic

Introduction Writing testbench is as complex as writing the RTL code itself. This days ASIC's are getting more and more complex and thus the challenge to verify this complex ASIC. Typically 60-70% of time in any ASIC is spent on verification/validation/testing. Even though above facts ar