首页|嵌入式系统|显示技术|模拟IC/电源|元件与制造|其他IC/制程|消费类电子|无线/通信|汽车电子|工业控制|医疗电子|测试测量
首页 > 分享下载 > 消费类电子 > xilinx时序约束培训教材

xilinx时序约束培训教材

资料介绍
xilinx时序约束培训教材Constraints
Practical Design for Xilinx!!

该文的版权归Xilinx公司所有! 由www.edacn.com收集整理。
Make EDA serve you!
Practical Design for Xilinx, Section 7, 12/29/98 Page 1

When to use Timing Constraints?
Constraints add to run time, so don’t use them unless you need to Faster designs need constraining
― it depends on the speed grade of the device selected, but in general, any design with a clock speed of 50MHz or less and a reasonable number of logic levels (7 or less), doesn’t need timing constraints ― designs over 50MHz should use timing constraints ― if you have a signal clock and are under the 50MHz limit above, you will not need timing constraints - you can always add them later if you need to ― these are paths where you know you have two or more clock cycles for logic to steadystate after an in……
标签:xilinx时序约束培训教材
xilinx时序约束培训教材
本地下载

评论