xilinx时序约束培训教材

xilinx时序约束培训教材Constraints
Practical Design for Xilinx!!

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Practical Design for Xilinx, Section 7, 12/29/98 Page 1

When to use Timing Constraints?
Constraints add to run time, so don’t use them unless you need to Faster designs need constraining
― it depends on the speed grade of the device selected, but in general, any design with a clock speed of 50MHz or less and a reasonable number of logic levels (7 or less), doesn’t need timing constraints ― designs over 50MHz should use timing constraints ― if you have a signal clock and are under the 50MHz limit above, you will not need timing constraints - you can always add them later if you need to ― these are paths where you know you have two or more clock cycles for logic to steadystate after an in