ADV202_input_tiling

ADV202_input_tiling_rev0ANALOG DEVICES

TN-0003 TECHNICAL NOTE

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Recommended HD Architectures using 4 ADV202 Chips
OVERVIEW
This document provides a recommended architectures for implementing HD JPEG2000 Capture/Playback systems that require 4 ADV202 chips in order to achieve the highest possible level of performance. For each of these architectures, it is assumed that the Luminance and Chrominance pixel interfaces are separate 10-bit buses (or 8bit buses), and each is sampled at 74.25 MHz. Thus, the chip conguration can be illustrated as such: FIGURE 1. Diagram of 4-chip ADV202 Conguration

ADV202 LUM1
Must connect common HSYNC, VSYNC, Pixel HOST and FIELD (HVF) to all 4 chips. Interface Interface