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施密特触发器详解Tri-State Logic and Schmitt Triggers
University of Connecticut
1
Tri-State Logic
n n
n
Three States: High, Low, High Z (high impedance, or disabled) Tri-state gates may be constructed using transmission gates, or by internal modifications to 2-state gates. Tri-state gates are required for bus-based architectures:
P
PIA
ROM
n - bit data bus
RAM
RAM
RAM
Many devices are connected in parallel on the bus, but only one device can attempt to drive the bus at one time.
University of Connecticut
2
Tri-State TTL NAND2 Gate
VCC
ENABLE = HIGH.
RP RB RC
QP
A QI B ENABLE DS DIA DIB DEN
QS
DO OUT
ENABLE = LOW.
QO RD
If the control input is inverted, it is called an “INHIBIT” input.
University of Connecticut 3
Tri-State CMOS Gate
VDD
ENABLE = HIGH.
MPI MPE MNI
MPO IN MNO OU
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