资料介绍
FPGA应用举例FPGA应用举例
七段译码器
LIBRARY IEEE; USE ENTITY seven_v IS PORT( D : S : END seven_v ; ARCHITECTURE a OF BEGIN PROCESS(D) BEGIN ？？？ END PROCESS; END a; IEEE.STD_LOGIC_1164.ALL; CASE D IS
WHEN 0 => S<="1111110"; --0 WHEN 1 => S<="0000110"; --1 IN INTEGER RANGE 0 TO 9; WHEN 2 => S<="1101101"; OUT STD_LOGIC_VECTOR(0 DOWNTO --2 6) ); WHEN 3 => S<="1111001"; --3 WHEN 4 => S<="0110011"; --4 seven_v WHEN IS 5 => S<="1011011"; --5 WHEN 6 => S<="1011111"; --6 WHEN 7 => S<="1110000"; --7 WHEN 8 => S<="1111111"; --8 WHEN 9 => S<="1111011"; --9 WHEN OTHERS => S<="0000000"; END CASE;
半加器－（不考虑低位的进位）
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY hadd_v IS PORT ( A, B : IN STD_LOGIC; S, C : OUT STD_LOGIC); END hadd_v; ARCHITECTURE a OF hadd_v IS SIGNAL temp : STD_LOGIC_VEC
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