资料介绍
Berrydale_Schematics_0p85
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Berrydale- Daughter Card for Mainstone Evaluation Platform Sheet
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Intel Confidential
Description Cover Sheet Block Diagram Bulverde Flash SDRAM Marathon Marathon Crystal Local Memory LAI MicroDIMM LCD1 LCD2/LCD3 LCD/GIB LAI System Bus LAI Tranceivers Mainboard Connector Reset / Straps JTAG / UART CPLD System Bus Resistors FPGA Switch / LEDs Ethernet 1/2 USB AC'97 Power Delivery Chip Select / Interrupt Map Default Stuffing Option Rev History
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B
A
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Title Size B Date:
Berrydale Daughter Card Document Number Tuesday, December 16, 2003 Sheet
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R ev 4.2 1 of 39
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Block Diagram
Marathon Clocks Sheet 11
Intel Confidential
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Bulverd
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